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1 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. 8mx64 flash 3.3v page mode simultaneous read/write operation multi-chip package access times of 70, 90, 100, 120ns packaging ? 159 pbga, 13x22mm ? 1.27mm pitch 1,000,000 erase/program cycles per sector page mode ? page size is 8 words: fast page read access from random locations within the page. sector architecture ? bank a (16mb): 4kw x 8 and 32 kw x 31 ? bank b (48mb): 32kw x 96 ? bank c (48mb): 32kw x 96 ? bank d (16mb): 4kw x 8 and 3kw x 31 both top and bottom boot blocks zero power operation organized as 8mx64, user con gurable as 2x8mx32 or 4x8mx16 commercial, industrial and military temperature ranges 3.3 volt for read, erase and write operations simultaneous read/write operations: ? data can be continuously read from one bank while executing erase/program functions in another bank ? zero latency between read and write operations erase suspend/resume ? suspends erase operations to allow read or programming in other sectors of same bank data polling and toggle bits ? provides a software method of detecting the status of program or erase cycles unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences ready/busy# output (ry/by#) ? hardware method for detecting program or erase cycle completion hardware reset pin (reset#) ? hardware method of resetting the internal state machine to the read mode wp#/acc input pin ? write protect (wp#) function allows protection of two outermost boot sector, regardless of sector protect status ? acceleration (acc) function accelerates program timing persistent sector protection ? a command sector protection method of locking combinations of individual sectors and sector groups to prevent program or erase operation within that sector password sector protection or cancellation ? a sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-de ned 64-bit password. * this product is subject to change without notice. features
2 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. we1# we2# we3# we4# cs4# cs3# cs2# cs1# ry/by# reset# oe# a 0-22 wp#/acc dq 16-31 dq 32-47 dq 48-63 dq 0-15 8m x 16 8m x 16 8m x 16 8m x 16 v io v io v cc gnd gnd gnd gnd gnd gnd v io v cc v io v cc v io gnd gnd dq33 dq40 dq32 cs 3 # oe# a2 a3 a4 dq 17 dq24 dq16 cs2# v cc gnd gnd dq41 dq43 dq35 dq42 dq34 a0 wp#/a cc a6 a17 we 2 # dq19 dq26 dq18 dq25 gnd gnd we 3 # dq45 dq37 dq44 dq36 a22 a11 a9 ry/by# dq29 dq21 dq28 dq20 dq27 gnd v cc v cc v cc v io v io dq47 dq39 dq46 dq38 v cc gnd v cc gnd dnu* dq31 dq23 dq30 dq22 v io dq 57 dq49 dq56 dq48 cs 4 # a12 v io gnd a14 dq9 dq1 dq8 dq0 cs 1 # v cc gnd dnu dq59 dq51 dq58 dq50 a16 a7 a1 a5 dq4 dq11 dq3 dq10 dq2 gnd gnd we 4 # dq61 dq53 dq60 dq52 a21 a10 reset# a18 we 1 # dq6 dq13 dq5 dq12 gnd gnd v cc dq63 dq55 dq62 dq54 a20 a15 a13 a8 a19 dq15 dq7 dq14 gnd gnd v io v cc v io v cc gnd gnd gnd* gnd gnd gnd v io v cc v io v cc v io a b c d e f g h j k l m n p r t 12345678910 block diagram pin description dq 0-63 data inputs/outputs a 0-22 address inputs we# 1-4 write enables cs# 1-4 chip selects oe# output enable reset# hardware reset wp#/acc hardware write protection/acceleration ry/by# ready/busy output v cc power supply v io i/o power supply gnd ground dnu do not use fig 1: pin configuration for w78m64v-xsbx (top view) * ball l5 is reserved for a23 for future upgrades.
3 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. general description the w78m64v-xsbx is a 512mb, 3.3 volt-only page mode and simultaneous read/write flash memory device. the device offers fast page access times allowing high speed microprocessors to operate without wait states. to eliminate bus contention the device has separate chip enable (cs#), write enable (we#) and output enable (oe#) controls. simultaneous read/write operation with zero latency. the simultaneous read/write architecture provides simultaneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. the device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). this releases the system from waiting for the completion of a program or erase operation, greatly improving system performance. the device can be organized in both top and bottom sector con gurations. the banks are organized as follows: jedec 42.4 single-power-supply flash standard . commands are written to the command register using standard microprocessor write timing. register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by executing the program command sequence. the unlock bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. device erasure occurs by executing the erase command sequence. the host system can detect whether a program or erase operation is complete by reading the dq7 (data# polling) and dq6 (toggle) status bits . after a program or erase cycle has been completed, the device is ready to read array data or accept another command. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. hardware data protection measures include a low v cc detector that automatically inhibits write operations during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. this can be achieved in-system or via programming equipment. the erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. if a read is needed from the secsi sector area (one time program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. the device offers two power-saving features. when addresses have been stable for a speci ed amount of time, the device enters the automatic sleep mode. the system can also place the device into the standby mode. power consumption is greatly reduced in both these modes. bank sectors a 16 mbit (4 kw x 8 and 32 kw x 31) b 48 mbit (32 kw x 96) c 48 mbit (32 kw x 96) d 16 mbit (4 kw x 8 and 32 kw x 31) page mode features the page size is 8 words. after initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page. standard flash memory features the device requires a 3.3 volt power supply for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. the device is entirely command set compatible with the
4 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. table 1. device bus operation 3 operation cs# oe# we# reset# wp#/acc addresses (a22-a0) dq15-dq0 read llh h x a in d out write lhl h x a in d in standby v io 0.3 v xxv io 0.3 v x (note 2) x high-z output disable l h h h x x high-z reset x x x l x x high-z temporary sector unprotect (high voltage xxxv id xa in d in legend : l = logic low = v il , h = logic high = v ih, v id = 11.5-12.5 v, v hh = 8.5-9.5 v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes : 1. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the high voltage se ctor protection section. 2. wp#/acc must be high when writing to sectors 0, 1, 268, or 269. 3. for each chip requirements for reading array data to read array data from the outputs, the system must drive the oe# and appropriate cs# pins to v il . cs# is the power control. oe# is the output control and gates array data to the output pins. we# should remain at v ih. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. each bank remains enabled for read access until the command register contents are altered. refer to the ac characteristics table for timing speci cations and to figure 11 for the timing diagram. i cc1 in the dc characteristics table represents the active current speci cation for reading array data. random read (non-page read) address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t cs ) is the delay from the stable addresses and stable cs# to valid data at the output inputs. the output enable access time is the delay from the falling edge of the oe# to valid data at the output inputs (assuming the addresses have been stable for at least t acc ?t oe time). page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read operation. this mode provides faster read access speed for random locations within a page. address bits a22?a3 select an 8 word page, and address bits a2?a0 select a speci c word within that page. this is an asynchronous operation with the microprocessor supplying the speci c word location. the random or initial page access is t acc or t cs and subsequent page read accesses (as long as the locations speci ed by the microprocessor falls within that page) is
5 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. equivalent to t pacc . when cs# is deasserted (cs#=v ih ), the reassertion of cs# for subsequent access has access time of t acc or t cs . here again, cs# selects the device and oe# is the output control and should be used to gate data to the output inputs if the device is selected. fast page mode accesses are obtained by keeping a22?a3 constant and changing a2?a0 to select the speci c word within that page. the device features an unlock bypass mode to facilitate faster programming. once a bank enters the unlock bypass mode, only two write cycles are required to program a word, instead of four. the ?word program command sequence? section has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sectors, or the entire device. table 4 indicates the address space that each sector occupies. a ?bank address? is the address bits required to uniquely select a bank. similarly, a ?sector address? refers to the address bits required to uniquely select a sector. the ?command de nitions? section has details on erasing a sector or the entire chip, or suspending/ resuming the erase operation. i cc2 in the dc characteristics table represents the active current speci cation for the write mode. the ac characteristics section contains timing speci cation tables and timing diagrams for write operations. accelerated program operation the device offers accelerated program operations through the a cc function. this function is primarily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device automatically enters the mentioned unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp#/acc pin returns the device to normal operation. note that v hh must not be asserted on wp#/acc for operations other than accelerated programming, or device damage may result. in addition, the wp#/acc pin should be raised to v cc when not in use. that is, the wp#/acc pin should not be left oating or unconnected; inconsistent behavior of the device may result. autoselect functions if the system writes the autoselect command sequence, the device enters the autoselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on dq63?dq0. standard read cycle timings apply in this mode. refer to the autoselect mode and autoselect command sequence sections for more information. table 2. page select word a2 a1 a0 word 0 0 0 0 word 1 0 0 1 word 2 0 1 0 word 3 0 1 1 word 4 1 0 0 word 5 1 0 1 word 6 1 1 0 word 7 1 1 1 simultaneous operation in addition to the conventional features (read, program, erase-suspend read, and erase-suspend program), the device is capable of reading data from one bank of memory while a program or erase operation is in progress in another bank of memory (simultaneous operation). the bank can be selected by bank addresses (a22?a20) with zero latency. the simultaneous operation can execute multi-function mode in the same bank. table 3. bank select bank a22-a20 bank a 000 bank b 001, 010, 011 bank c 100, 101, 110 bank d 111 writing commands/command sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive we# and cs# to v il , and oe# to v ih .
6 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the cs# and reset# pins are both held at v io 0.3 v. if cs# and reset# are held at v ih , but not within v io 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t cs ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. i cc3 in the dc characteristics table represents the cmos standby current speci cation. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the device automatically enables this mode when addresses remain stable for t acc + 150 ns. the automatic sleep mode is independent of the cs#, we#, and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. note that during automatic sleep mode, oe# must be at v ih before the device reduces current to the stated sleep mode speci cation. i cc 5 in the dc characteristics table represents the automatic sleep mode current speci cation. reset#: hardware reset pin the reset# pin provides a hardware method of resetting the device to reading array data. when the reset# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc 4). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up rmware from the flash memory. if reset# is asserted during a program or erase operation, the ry/by# pin remains a ?0? (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/ by# to determine whether the reset operation is complete. if reset# is asserted when a program or erase operation is not executing (ry/by# pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algorithms). the system can read data t rh after the reset# pin returns to v ih . refer to the ac characteristic tables for reset# parameters and to figure 14 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins (except for ry/by#) are placed in the highest impedance state.
7 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. bank sector sector address (a22-a12) sector size (kwords) address range (x16) bank a sa0 00000000000 4 000000h-000fffh sa1 00000000001 4 001000h-001fffh sa2 00000000010 4 002000h-002fffh sa3 00000000011 4 003000h-003fffh sa4 00000000100 4 004000h-004fffh sa5 00000000101 4 005000h-005fffh sa6 00000000110 4 006000h-006fffh sa7 00000000111 4 007000h-007fffh sa8 00000001xxx 32 008000h-00ffffh sa9 00000010xxx 32 010000h-017fffh sa10 00000011xxx 32 018000h-01ffffh sa11 00000100xxx 32 020000h-027fffh sa12 00000101xxx 32 028000h-02ffffh sa13 00000110xxx 32 030000h-037fffh sa14 00000111xxx 32 038000h-03ffffh sa15 00001000xxx 32 040000h-047fffh sa16 00001001xxx 32 048000h-04ffffh sa17 00001010xxx 32 050000h-057fffh sa18 00001011xxx 32 058000h-05ffffh sa19 00001100xxx 32 060000h-067fffh sa20 00001101xxx 32 068000h-06ffffh sa21 00001110xxx 32 070000h-077fffh sa22 0000 1111xxx 32 078000h-07ffffh sa23 00010000xxx 32 080000h-087fffh sa24 00010001xxx 32 088000h-08ffffh sa25 00010010xxx 32 090000h-097fffh sa26 00010011xxx 32 098000h-09ffffh sa27 00010100xxx 32 0a0000h-0a7fffh sa28 00010101xxx 32 0a8000h-0affffh sa29 00010110xxx 32 0b0000h-0b7fffh sa30 00010111xxx 32 0b8000h-0bffffh sa31 00011000xxx 32 0c0000h-0c7fffh sa32 00011001xxx 32 0c8000h-0cffffh sa33 00011010xxx 32 0d0000h-0d7fffh sa34 00011011xxx 32 0d8000h-0dffffh sa35 00011100xxx 32 0e0000h-0e7fffh sa36 00011101xxx 32 0e8000h-0effffh sa37 000 11110xxx 32 0f0000h-0f7fffh sa38 000 11111xxx 32 0f8000h-0fffffh table 4. sector architecture
8 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. bank sector sector address (a22-a12) sector size (kwords) address range (x16) bank b sa39 00100000xxx 32 100000h?107fffh sa40 00100001xxx 32 108000h?10ffffh sa41 00100010xxx 32 110000h?117fffh sa42 00100011xxx 32 118000h?11ffffh sa43 00100100xxx 32 120000h?127fffh sa44 00100101xxx 32 128000h?12ffffh sa45 00100110xxx 32 130000h?137fffh sa46 00100111xxx 32 138000h?13ffffh sa47 00101000xxx 32 140000h?147fffh sa48 00101001xxx 32 148000h?14ffffh sa49 00101010xxx 32 150000h?157fffh sa50 00101011xxx 32 158000h?15ffffh sa51 00101100xxx 32 160000h?167fffh sa52 00101101xxx 32 168000h?16ffffh sa53 00101110xxx 32 170000h?177fffh sa54 00101111xxx 32 178000h?17ffffh sa55 00110000xxx 32 180000h?187fffh sa56 00110001xxx 32 188000h?18ffffh sa57 00110010xxx 32 190000h?197fffh sa58 00110011xxx 32 198000h?19ffffh sa59 00110100xxx 32 1a0000h?1a7fffh sa60 00110101xxx 32 1a8000h?1affffh sa61 00110110xxx 32 1b0000h?1b7fffh sa62 00110111xxx 32 1b8000h?1bffffh sa63 00111000xxx 32 1c0000h?1c7fffh sa64 00111001xxx 32 1c8000h?1cffffh sa65 00111010xxx 32 1d0000h?1d7fffh sa66 00111011xxx 32 1d8000h?1dffffh sa67 00 1111 00xxx 32 1e0000h?1e7fffh sa68 00 1111 01xxx 32 1e8000h?1effffh sa69 00 1111 10xxx 32 1f0000h?1f7fffh sa70 00 11111 1xxx 32 1f8000h?1fffffh sa71 01000000xxx 32 200000h?207fffh sa72 01000001xxx 32 208000h?20ffffh sa73 01000010xxx 32 210000h?217fffh sa74 01000011xxx 32 218000h?21ffffh sa75 01000100xxx 32 220000h?227fffh sa76 01000101xxx 32 228000h?22ffffh sa77 01000110xxx 32 230000h?237fffh sa78 01000111xxx 32 238000h?23ffffh table 4. sector architecture
9 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. bank sector sector address (a22-a12) sector size (kwords) address range (x16) bank b sa79 01001000xxx 32 240000h?247fffh sa80 01001001xxx 32 248000h?24ffffh sa81 01001010xxx 32 250000h?257fffh sa82 01001011xxx 32 258000h?25ffffh sa83 01001100xxx 32 260000h?267fffh sa84 01001101xxx 32 268000h?26ffffh sa85 01001110xxx 32 270000h?277fffh sa86 01001111xxx 32 278000h?27ffffh sa87 01010000xxx 32 280000h?287fffh sa88 01010001xxx 32 288000h?28ffffh sa89 01010010xxx 32 290000h?297fffh sa90 01010011xxx 32 298000h?29ffffh sa91 01010100xxx 32 2a0000h?2a7fffh sa92 01010101xxx 32 2a8000h?2affffh sa93 01010110xxx 32 2b0000h?2b7fffh sa94 01010111xxx 32 2b8000h?2bffffh sa95 01011000xxx 32 2c0000h?2c7fffh sa96 01011001xxx 32 2c8000h?2cffffh sa97 01011010xxx 32 2d0000h?2d7fffh sa98 01011011xxx 32 2d8000h?2dffffh sa99 01011100xxx 32 2e0000h?2e7fffh sa100 01011101xxx 32 2e8000h?2effffh sa101 01011110xxx 32 2f0000h?2f7fffh sa102 010 1111 1xxx 32 2f8000h?2fffffh sa103 01100000xxx 32 300000h?307fffh sa104 01100001xxx 32 308000h?30ffffh sa105 01100010xxx 32 310000h?317fffh sa106 01100011xxx 32 318000h?31ffffh sa107 01100100xxx 32 320000h?327fffh sa108 01100101xxx 32 328000h?32ffffh sa109 01100110xxx 32 330000h?337fffh sa110 01100111xxx 32 338000h?33ffffh sa111 01101000xxx 32 340000h?347fffh sa112 01101001xxx 32 348000h?34ffffh sa113 01101010xxx 32 350000h?357fffh sa114 01101011xxx 32 358000h?35ffffh sa115 01101100xxx 32 360000h?367fffh sa116 01101101xxx 32 368000h?36ffffh sa117 01101110xxx 32 370000h?377fffh sa118 01101111xxx 32 378000h?37ffffh table 4. sector architecture
10 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. table 4. sector architecture bank sector sector address (a22-a12) sector size (kwords) address range (x16) bank b sa119 01110000xxx 32 380000h?387fffh sa120 01110001xxx 32 388000h?38ffffh sa121 01110010xxx 32 390000h?397fffh sa122 01110011xxx 32 398000h?39ffffh sa123 01110100xxx 32 3a0000h?3a7fffh sa124 01110101xxx 32 3a8000h?3affffh sa125 01110110xxx 32 3b0000h?3b7fffh sa126 01110111xxx 32 3b8000h?3bffffh sa127 0 1111000xxx 32 3c0000h?3c7fffh sa128 0 1111001xxx 32 3c8000h?3cffffh sa129 0 1111010xxx 32 3d0000h?3d7fffh sa130 0 111101 1xxx 32 3d8000h?3dffffh sa131 0 11111 00xxx 32 3e0000h?3e7fffh sa132 0 11111 01xxx 32 3e8000h?3effffh sa133 0 11111 10xxx 32 3f0000h?3f7fffh sa134 0 111111 1xxx 32 3f8000h?3fffffh bank c sa135 10000000xxx 32 400000h?407fffh sa136 10000001xxx 32 408000h?40ffffh sa137 10000010xxx 32 410000h?417fffh sa138 10000011xxx 32 418000h?41ffffh sa139 10000100xxx 32 420000h?427fffh sa140 10000101xxx 32 428000h?42ffffh sa141 10000110xxx 32 430000h?437fffh sa142 10000111xxx 32 438000h?43ffffh sa143 10001000xxx 32 440000h?447fffh sa144 10001001xxx 32 448000h?44ffffh sa145 10001010xxx 32 450000h?457fffh sa146 10001011xxx 32 458000h?45ffffh sa147 10001100xxx 32 460000h?467fffh sa148 10001101xxx 32 468000h?46ffffh sa149 10001110xxx 32 470000h?477fffh sa150 10001111xxx 32 478000h?47ffffh sa151 10010000xxx 32 480000h?487fffh sa152 10010001xxx 32 488000h?48ffffh sa153 10010010xxx 32 490000h?497fffh sa154 10010011xxx 32 498000h?49ffffh sa155 10010100xxx 32 4a0000h?4a7fffh sa156 10010101xxx 32 4a8000h?4affffh sa157 10010110xxx 32 4b0000h?4b7fffh sa158 10010111xxx 32 4b8000h?4bffffh
11 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. table 4. sector architecture bank sector sector address (a22-a12) sector size (kwords) address range (x16) bank c sa159 10011000xxx 32 4c0000h?4c7fffh sa160 10011001xxx 32 4c8000h?4cffffh sa161 10011010xxx 32 4d0000h?4d7fffh sa162 10011011xxx 32 4d8000h?4dffffh sa163 10011100xxx 32 4e0000h?4e7fffh sa164 10011101xxx 32 4e8000h?4effffh sa165 100 11110xxx 32 4f0000h?4f7fffh sa166 100 1111 1xxx 32 4f8000h?4fffffh sa167 10100000xxx 32 500000h?507fffh sa168 10100001xxx 32 508000h?50ffffh sa169 10100010xxx 32 510000h?517fffh sa170 10100011xxx 32 518000h?51ffffh sa171 10100100xxx 32 520000h?527fffh sa172 10100101xxx 32 528000h?52ffffh sa173 10100110xxx 32 538000h?53ffffh sa175 10101000xxx 32 540000h?547fffh sa176 10101001xxx 32 548000h?54ffffh sa177 10101010xxx 32 550000h?557fffh sa178 10101011xxx 32 558000h?15ffffh sa179 10101100xxx 32 560000h?567fffh sa180 10101101xxx 32 568000h?56ffffh sa181 10101110xxx 32 570000h?577fffh sa182 10101111xxx 32 578000h?57ffffh sa183 10110000xxx 32 580000h?587fffh sa184 10110001xxx 32 588000h?58ffffh sa185 10110010xxx 32 590000h?597fffh sa186 10110011xxx 32 598000h?59ffffh sa187 10110100xxx 32 5a0000h?5a7fffh sa188 10110101xxx 32 5a8000h?5affffh sa189 10110110xxx 32 5b0000h?5b7fffh sa190 10110111xxx 32 5b8000h?5bffffh sa191 10111000xxx 32 5c0000h?5c7fffh sa192 10111001xxx 32 5c8000h?5cffffh sa193 10111010xxx 32 5d0000h?5d7fffh sa194 10111011xxx 32 5d8000h?5dffffh sa195 10111100xxx 32 5e0000h?5e7fffh sa196 10111101xxx 32 5e8000h?5effffh sa197 101 11110xxx 32 5f0000h?5f7fffh sa198 101 1111 1xxx 32 5f8000h?5fffffh
12 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. table 4. sector architecture bank sector sector address (a22-a12) sector size (kwords) address range (x16) bank c sa199 11000000xxx 32 600000h?607fffh sa200 11000001xxx 32 608000h?60ffffh sa201 11000010xxx 32 610000h?617fffh sa202 11000011xxx 32 618000h?61ffffh sa203 11000100xxx 32 620000h?627fffh sa204 11000101xxx 32 628000h?62ffffh sa205 11000110xxx 32 630000h?637fffh sa206 11000111xxx 32 638000h?63ffffh sa208 11001001xxx 32 648000h?64ffffh sa209 11001010xxx 32 650000h?657fffh sa210 11001011xxx 32 658000h?65ffffh sa211 11001100xxx 32 660000h?667fffh sa212 11001101xxx 32 668000h?66ffffh sa213 11001110xxx 32 670000h?677fffh sa214 1100 1111xxx 32 678000h?67ffffh sa215 11010000xxx 32 680000h?687fffh sa216 11010001xxx 32 688000h?68ffffh sa217 11010010xxx 32 690000h?697fffh sa218 11010011xxx 32 698000h?69ffffh sa219 11010100xxx 32 6a0000h?6a7fffh sa220 11010101xxx 32 6a8000h?6affffh sa221 11010110xxx 32 6b0000h?6b7fffh sa222 11010111xxx 32 6b8000h?6bffffh sa223 11011000xxx 32 6c0000h?6c7fffh sa224 11011001xxx 32 6c8000h?6cffffh sa225 11011010xxx 32 6d0000h?6d7fffh sa226 11011011xxx 32 6d8000h?6dffffh sa227 11011100xxx 32 6e0000h?6e7fffh sa228 11011101xxx 32 6e8000h?6effffh sa229 110 11110xxx 32 6f0000h?6f7fffh sa230 110 1111 1xxx 32 6f8000h?6fffffh
13 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. table 4. sector architecture bank sector sector address (a22-a12) sector size (kwords) address range (x16) bank d sa231 11100000xxx 32 700000h-707fffh sa232 11100001xxx 32 708000h-70ffffh sa233 11100010xxx 32 710000h-717fffh sa234 11100011xxx 32 718000h-71ffffh sa235 11100100xxx 32 720000h-727fffh sa236 11100101xxx 32 728000h-72ffffh sa237 11100110xxx 32 730000h-737fffh sa238 11100111xxx 32 738000h-73ffffh sa239 11101000xxx 32 740000h-747fffh sa240 11101001xxx 32 748000h-74ffffh sa241 11101010xxx 32 750000h-757fffh sa242 11101011xxx 32 758000h-75ffffh sa243 11101100xxx 32 760000h-767fffh sa244 11101101xxx 32 768000h-76ffffh sa245 11101110xxx 32 770000h-777fffh sa246 1110 1111xxx 32 778000h-77ffffh sa247 1111 0000xxx 32 780000h-787fffh sa248 1111 0001xxx 32 788000h-78ffffh sa249 1111 0010xxx 32 790000h-797fffh sa250 11110011xxx 32 798000h-79ffffh sa251 1111 0100xxx 32 7a0000h-7a7fffh sa252 1111 0101xxx 32 7a8000h-7affffh sa253 11110110xxx 32 7b0000h-7b7fffh sa254 11110111xxx 32 7b8000h-7bffffh sa255 1111 1000xxx 32 7o0000h-7c7fffh sa256 1111 1001xxx 32 7c8000h-7cffffh sa257 1111 1010xxx 32 7d0000h-7d7fffh sa258 1111101 1xxx 32 7d8000h-7dffffh sa259 11111 100xxx 32 7e0000h-7e7fffh sa260 11111 101xxx 32 7e8000h-7effffh sa261 111111 10xxx 32 7f0000h-7f7fffh sa262 1111111 1000 4 7f8000h-7f8fffh sa263 1111111 1001 4 7f9000h-7f9fffh sa264 1111111 1010 4 7fa000h-7fafffh sa265 11111111011 4 7fb000h-7fbfffh sa266 11111111100 4 7fo000h-7fcfffh sa267 11111111101 4 7fd000h-7fdfffh sa268 11111111110 4 7fe000h-7fefffh sa269 11111111111 4 7ff000h-7fffffh
14 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. table 5. secsi tm sector addresses sector size address range device 128 words 000000h?00007fh factory-locked area 64 words 000000h-00003fh customer-lockable area 64 words 000040h-00007fh autoselect mode the autoselect mode provides manufacturer and device identi cation, and sector protection veri cation, through identi er codes output on dq7?dq0 for each chip. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id on address pin a9. address pins must be as shown in table 6 . in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see ta b l e 4 ). table 6 shows the remaining address bits that are don?t care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identi er code on dq7?dq0. however, the autoselect codes can also be accessed in-system through the command register, for instances when the device is erased or programmed in a system without access to high voltage on the a9 pin. the command sequence is illustrated in table 13 . note that if a bank address (ba) on address bits a22?a20 is asserted during the third write cycle of the autoselect command, the host system can read autoselect data that bank and then immediately read array data from the other bank, without exiting the autoselect mode. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in table 13 . this method does not require v id . refer to the autoselect command sequence section for more information. table 6. autoselect codes (high voltage method) description cs# oe# we# a22 to a12 a10 a9 a8 a7 a6 a5 to a4 a3 a2 a1 a0 dq15 to dq0 (each chip) manufacturer id: l l h x x v id x l l x l l l l 0004h device id read cycle 1 llhxxv id x l l l l l l h 227eh read cycle 2 l h h h l 2220 read cycle 3 l h h h h 2200h sector protection veri cation llhsaxv id x l l l l l h l 0001h (protected), 0000h (unprotected) secsi indicator bit (dq7, dq6) llhxxv id x x l x l l h h 00c0h (factory and user locked) legend: l = logic low = v il , h = logic high = v ih , ba = bank address, sa = sector address, x = don?t care. note: the autoselect codes may also be accessed in-system via command sequences
15 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. table 7. boot sector/sector block addresses for protection/ unprotection sector a22-a12 sector/ sector block size sa0 00000000000 4 kwords sa1 00000000001 4 kwords sa2 00000000010 4 kwords sa3 00000000011 4 kwords sa4 00000000100 4 kwords sa5 00000000101 4 kwords sa6 00000000110 4 kwords sa7 00000000111 4 kwords sa8-sa10 00000001xxx 00000010xxx 00000011xxx 96 (3x32) kwords sa11-sa14 000001xxxxx 128 (4x32) kwords sa15-sa18 000010xxxxx 128 (4x32) kwords sa19-sa22 000011xxxxx 128 (4x32) kwords sa23-sa26 000100xxxxx 128 (4x32) kwords sa27-sa30 000101xxxxx 128 (4x32) kwords sa31-sa34 000110xxxxx 128 (4x32) kwords sa35-sa38 000111xxxxx 128 (4x32) kwords sa39-sa42 001000xxxxx 128 (4x32) kwords sa43-sa46 001001xxxxx 128 (4x32) kwords sa47-sa50 001010xxxxx 128 (4x32) kwords sa51-sa54 001011xxxxx 128 (4x32) kwords sa55-sa58 001100xxxxx 128 (4x32) kwords sa59-sa62 001101xxxxx 128 (4x32) kwords sa63-sa66 001110xxxxx 128 (4x32) kwords sa67-sa70 00 1111xxxxx 128 (4x32) kwords sa71-sa74 010000xxxxx 128 (4x32) kwords sa75-sa78 010001xxxxx 128 (4x32) kwords sa79-sa82 010010xxxxx 128 (4x32) kwords sa83-sa86 010011xxxxx 128 (4x32) kwords sa87-sa90 010100xxxxx 128 (4x32) kwords sa91-sa94 010101xxxxx 128 (4x32) kwords sa95-sa98 010110xxxxx 128 (4x32) kwords sa99-sa102 010111xxxxx 128 (4x32) kwords sa103-sa106 011000xxxxx 128 (4x32) kwords sa107-sa110 011001xxxxx 128 (4x32) kwords sa111-sa114 011010xxxxx 128 (4x32) kwords sa115-sa118 011011xxxxx 128 (4x32) kwords sa119-sa122 011100xxxxx 128 (4x32) kwords sa123-sa126 011101xxxxx 128 (4x32) kwords sa127-sa130 0 11110xxxxx 128 (4x32) kwords sector a22-a12 sector/ sector block size sa131-sa134 0 1111 1xxxxx 128 (4x32) kwords sa135-sa138 100000xxxxx 128 (4x32) kwords sa139-sa142 100001xxxxx 128 (4x32) kwords sa143-sa146 100010xxxxx 128 (4x32) kwords sa147-sa150 100011xxxxx 128 (4x32) kwords sa151-sa154 100100xxxxx 128 (4x32) kwords sa155-sa158 100101xxxxx 128 (4x32) kwords sa159-sa162 100110xxxxx 128 (4x32) kwords sa163-sa166 100111xxxxx 128 (4x32) kwords sa167-sa170 101000xxxxx 128 (4x32) kwords sa171-sa174 101001xxxxx 128 (4x32) kwords sa175-sa178 101010xxxxx 128 (4x32) kwords sa179-sa182 101011xxxxx 128 (4x32) kwords sa183-sa186 101100xxxxx 128 (4x32) kwords sa187-sa190 101101xxxxx 128 (4x32) kwords sa191-sa194 101110xxxxx 128 (4x32) kwords sa195-sa198 101111xxxxx 128 (4x32) kwords sa199-sa202 110000xxxxx 128 (4x32) kwords sa203-sa206 110001xxxxx 128 (4x32) kwords sa207-sa210 110010xxxxx 128 (4x32) kwords sa211-sa214 110011xxxxx 128 (4x32) kwords sa215-sa218 110100xxxxx 128 (4x32) kwords sa219-sa222 110101xxxxx 128 (4x32) kwords sa223-sa226 110110xxxxx 128 (4x32) kwords sa227-sa230 110111xxxxx 128 (4x32) kwords sa231-sa234 111000xxxxx 128 (4x32) kwords sa235-sa238 111001xxxxx 128 (4x32) kwords sa239-sa242 111010xxxxx 128 (4x32) kwords sa243-sa246 111011xxxxx 128 (4x32) kwords sa247-sa250 111100xxxxx 128 (4x32) kwords sa251-sa254 111101xxxxx 128 (4x32) kwords sa255-sa258 1111 10xxxxx 128 (4x32) kwords sa259-sa261 11111 100xxx 11111 101xxx 111111 10xxx 96 (3x32) kwords sa262 1111111 1000 4 kwords sa263 1111111 1001 4 kwords sa264 1111111 1010 4 kwords sa265 11111111011 4 kwords sa266 11111111100 4 kwords sa267 11111111101 4 kwords sa268 11111111110 4 kwords sa269 11111111111 4 kwords
16 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. sector protection the device features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: persistent sector protection a command sector protection method that replaces the old 12 v controlled protection method. password sector protection a highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted wp# hardware protection a write protect pin that can prevent program or erase operations in sectors 0, 1, 268, and 269. the wp# hardware protection feature is always available, independent of the software managed protection method chosen. selecting a sector protection mode all parts default to operate in the persistent sector protection mode. the user must then choose if the persistent or password protection method is most desirable. there are two one-time programmable non-volatile bits that de ne which sector protection method will be used. if the persistent sector protection method is desired, programming the persistent sector protection mode locking bit permanently sets the device to the persistent sector protection mode. if the password sector protection method is desired, programming the password mode locking bit permanently sets the device to the password sector protection mode. it is not possible to switch between the two protection modes once a locking bit has been set. one of the two modes must be selected when the device is rst programmed . this prevents a program or virus from later setting the password mode locking bit, which would cause an unexpected shift from the default persistent sector protection mode into the password protection mode. the device is shipped with all sectors unprotected. it is possible to determine whether a sector is protected or unprotected. see autoselect mode for details. persistent sector protection the persistent sector protection method replaces the 12 v controlled protection method in previous wedc ash devices. this new method provides three different sector protection states: persistently locked?the sector is protected and cannot be changed. dynamically locked?the sector is protected and can be changed by a simple command. unlocked?the sector is unprotected and can be changed by a simple command. to achieve these states, three types of ?bits? are used: persistent protection bit (ppb) a single persistent (non-volatile) protection bit is assigned to a maximum four sectors (see the sector address tables for speci c sector protection groupings). all 4 kword boot- block sectors have individual sector persistent protection bits (ppbs) for greater exibility. each ppb is individually modi able through the ppb write command. the device erases all ppbs in parallel. if any ppb requires erasure, the device must be instructed to preprogram all of the sector ppbs prior to ppb erasure. otherwise, a previously erased sector ppbs can potentially be over- erased. the ash device does not have a built-in means of preventing sector ppbs over-erasure. persistent protection bit lock (ppb lock) the persistent protection bit lock (ppb lock) is a global volatile bit. when set to ?1?, the ppbs cannot be changed. when cleared (?0?), the ppbs are changeable. there is only one ppb lock bit per device. the ppb lock is cleared after power-up or hardware reset. there is no command sequence to unlock the ppb lock. dynamic protection bit (dyb) a volatile protection bit is assigned for each sector. after power-up or hardware reset, the contents of all dybs is ?0?. each dyb is individually modi able through the dyb write command. when the parts are rst shipped, the ppbs are cleared, the dybs are cleared, and ppb lock is defaulted to power up in the cleared state ? meaning the ppbs are changeable. when the device is rst powered on the dybs power up cleared (sectors not protected). the protection state for each sector is determined by the logical or of the ppb and the dyb related to that sector. for the sectors that have the ppbs cleared, the dybs control whether or not the sector is protected or unprotected. by issuing the dyb write
17 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. command sequences, the dybs will be set or cleared, thus placing each sector in the protected or unprotected state. these are the so-called dynamic locked or unlocked states. they are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. this allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. the dybs maybe set or cleared as often as needed. the ppbs allow for a more static, and dif cult to change, level of protection. the ppbs retain their state across power cycles because they are non-volatile. individual ppbs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. the ppbs are also limited to 100 erase cycles. the ppb lock bit adds an additional level of protection. once all ppbs are programmed to the desired settings, the ppb lock may be set to ?1?. setting the ppb lock disables all program and erase commands to the non-volatile ppbs. in effect, the ppb lock bit locks the ppbs into their current state. the only way to clear the ppb lock is to go through a power cycle. system boot code can determine if any changes to the ppb are needed; for example, to allow new system code to be downloaded. if no changes are needed then the boot code can set the ppb lock to disable any further changes to the ppbs during system operation. the wp#/acc write protect pin adds a final level of hardware protection to sectors 0, 1, 268, and 269. when this pin is low it is not possible to change the contents of these sectors. these sectors generally hold system boot code. the wp#/acc pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. it is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. the sectors in the dynamic state are all unprotected. if there is a need to protect some of them, a simple dyb write command sequence is all that is necessary. the dyb write command for the dynamic sectors switch the dybs to signify protected and unprotected, respectively. if there is a need to change the status of the persistently locked sectors, a few more steps are required. first, the ppb lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. the ppbs can then be changed to re ect the desired settings. setting the ppb lock bit once again will lock the ppbs, and the device operates normally again. the best protection is achieved by executing the ppb lock bit set command early in the boot code, and protect the boot code by holding wp#/acc = v il . table 8. sector protection schemes dyb ppb ppb lock sector state 0 0 0 unprotected - ppb and dyb are changeable 0 0 1 unprotected - ppb not changeable, dyb is changeable 0 1 0 protected - ppb and dyb are changeable 100 110 0 1 1 protected - ppb not changeable, dyb is changeable 101 111 table 8 contains all possible combinations of the dyb, ppb, and ppb lock relating to the status of the sector in summary, if the ppb is set, and the ppb lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the ppb lock. if the ppb is cleared, the sector can be dynamically locked or unlocked. the dyb then controls whether or not the sector is protected or unprotected. if the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. a program command to a protected sector enables status polling for approximately 1 s beforethe device returns to read mode without having modi ed the contents of the protected sector. an erase command to a protected sector enables status polling for approximately 50 s after which the device returns to read mode without having erased the protected sector. the programming of the dyb, ppb, and ppb lock for a given sect or can be ver i f ied by writing a dyb/ppb/ppb lock verify command to the device. persistent sector protection mode locking bit like the password mode locking bit, a persistent sector protection mode locking bit exists to guarantee that the device remain in software sector protection. once set, the persistent sector protection locking bit prevents programming of the password protection mode locking bit. this guarantees that a hacker could not place the device in password protection mode.
18 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. password protection mode the password sector protection mode method allows an even higher level of security than the persistent sector protection mode. there are two main differences between the persistent sector protection and the password sector protection mode: when the device is rst powered on, or comes out of a reset cycle, the ppb lock bit set to the locked state, rather than cleared to the unlocked state. the only means to clear the ppb lock bit is by writing a unique 64-bit password to the device. the password sector protection method is otherwise identical to the persistent sector protection method. a 64-bit password is the only additional tool utilized in this method. once the password mode locking bit is set, the password is permanently set with no means to read, program, or erase it. the password is used to clear the ppb lock bit. the password unlock command must be written to the ash, along with a password. the ash device internally compares the given password with the pre-programmed password. if they match, the ppb lock bit is cleared, and the ppbs can be altered. if they do not match, the ash device does nothing. there is a built-in 2 s delay for each ?password check.? this delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. password and password mode locking bit in order to select the password sector protection scheme, the customer must first program the password. the password may be correlated to the unique electronic serial number (esn) of the particular ash device. each esn is different for every ash device; therefore each password should be different for every ash device. while programming in the password region, the customer may perform password verify operations. once the desired password is programmed in, the customer must then set the password mode locking bit. this operation achieves two objectives: 1. permanently sets the device to operate using the password protection mode. it is not possible to reverse this function. 2. disables all further commands to the password region. all program, and read operations are ignored. both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. the user must be sure that the password protection method is desired when setting the password mode locking bit. more importantly, the user must be sure that the password is correct when the password mode locking bit is set. due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. if the password is lost after setting the password mode locking bit, there will be no way to clear the ppb lock bit. the password mode locking bit, once set, prevents reading the 64-bit password on the dq bus and further password programming. the password mode locking bit is not erasable. once password mode locking bit is programmed, the persistent sector protection locking bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit password the 64-bit password is located in its own memory space and is accessible through the use of the password program and verify commands (see ?password verify command?). the password function works in conjunction with the password mode locking bit, which when set, prevents the password verify command from reading the contents of the password on the pins of the device. write protect (wp#) the write protect feature provides a hardware method of protecting sectors 0, 1, 268, and 269 without using v id . this function is provided by the wp# pin and overrides the previously discussed high voltage sector protection method. if the system asserts v il on the wp#/acc pin, the device disables program and erase functions in the two outermost 4 kword sectors on both ends of the ash array independent of whether it was previously protected or unprotected. if the system asserts v ih on the wp#/acc pin, the device reverts to whether sectors 0, 1, 268, and 269 were last set to be protected or unprotected. that is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in high voltage sector protection . note that the wp#/acc pin must not be left oating or unconnected; inconsistent behavior of the device may result.
19 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. persistent protection bit lock the persistent protection bit (ppb) lock is a volatile bit that re ects the state of the password mode locking bit after power-up reset. if the password mode lock bit is also set after a hardware reset (reset# asserted) or a power-up reset, the only means for clearing the ppb lock bit in password protection mode is to issue the password unlock command. successful execution of the password unlock command clears the ppb lock bit, allowing for sector ppbs modi cations. asserting reset#, taking the device through a power-on reset, or issuing the ppb lock bit set command sets the ppb lock bit to a ?1? when the password mode lock bit is not set. if the password mode locking bit is not set, including persistent protection mode, the ppb lock bit is cleared after power-up or hardware reset. the ppb lock bit is set by issuing the ppb lock bit set command. once set the only means for clearing the ppb lock bit is by issuing a hardware or power-up reset. the password unlock command is ignored in persistent protection mode. high voltage sector protection sector protection and unprotection may also be implemented using programming equipment. the procedure requires high voltage (v id ) to be placed on the reset# pin. refer to figure 2 for details on this procedure. note that for sector unprotect, all unprotected sectors must rst be protected prior to the rst sector write cycle.
20 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. sector protect: write 60h to sector address with a7-a0 = 00000010 set up sector address wait 100 s verify sector protect: write 40h to sector address with a7-a0 = 00000010 read from sector address with a7-a0 = 00000010 start plscnt = 1 reset# = v id wait 4 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a7-a0 = 01000010 set up first sector address wait 1.2 ms verify sector unprotect: write 40h to sector address with a7-a0 = 00000010 read from sector address with a7-a0 = 00000010 start plscnt = 1 reset# = v id wait 4 s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1 remove v id from reset# write reset command sector protect complete remove v id from reset# write reset command sector unprotect complete figure 2. in-system sector protection/sector unprotection algorithms
21 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. temporary sector unprotect this feature allows temporary unprotection of previously protected sectors to change data in-system. the sector unprotect mode is activated by setting the reset# pin to v id . during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once v id is removed from the reset# pin, all the previously protected sectors are protected again. figure 3 shows the algorithm, and figure 24 shows the timing diagrams, for this feature. while ppb lock is set, the device cannot enter the temporary sector unprotection mode. secsi sector is divided into 64 factory-lockable words that can be programmed and locked by the user. the secsi sector is located at addresses 000000h-00007fh in both persistent protection mode and password protection mode. it uses indicator bits (dq6, dq7) to indicate the factory- locked and user-locked status of the part. the system accesses the secsi sector through a command sequence (see ?enter secsi? sector/exit secsi sector command sequence?). after the sysem has written the enter secsi sector command sequence, it may read the secsi sector by using the addresses normally occupied by the boot sectors. this mode of operation continues until the system issues the exit secsi sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. note that the acc function and unlock bypass modes are not available when the secsi sector is enabled. factory-locked area (64 words) the factory-locked area of the secsi sector (000000h- 00003fh) is locked when the part is shipped, whether or not the area was programmed at the factory. the secsi sector factory-locked indicator bit (dq7) is permanently set to a ?1?. user-lockable area (64 words) the user-lockable area of the secsi sector (000040h- 00007eh) is shipped unprotected, which allows the user to program and optionally lock the area as appropriate for the application. the secsi sector user-locked indicator bit (dq6) is shipped as ?0? and can be permanently locked to ?1? by issuing the secsi protection bit program command. the secsi sector can be read any number of times, but can be programmed and locked only once. note that the accelerated programming (acc) and unlock bypass functions are not available when programming the secsi sector. the user-lockable secsi sector area can be protected using one of the following procedures: follow the secsi sector protection agorithm as shown in figure 4. this allows in-system protection of the secsi sector without raising any device pin to a high voltage. note that this method is only appliacable to the secsi sector. to verify the protect/unprotect status of the secsi sector, follow the algorithm shown in figure 5 . secsi? (secured silicon) sector flash memory region the secsi (secured silicon) sector feature provides a flash memory region that enables permanent part identi cation through an electronic serial number (esn) the 128-word start perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2) reset# = v id (note 1) figure 3. temporary sector unprotect operation notes: 1. all protected sectors unprotected (if wp#/acc = vil, sectors 0, 1, 268, 269 will remain protected). 2. all previously protected sectors are protected once again
22 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. start secsi sector entry write aah to address 555h write 55h to address 2aah write 88h to a address 555h tm secsi sector protection entry write aah to address 555h write 55h to address 2aah write 60h to a address 555h plscnt = 1 protect secsi sector: write 68h to sector address with a7-a0 = 00011010 time out 256 s verify secsi sector: write 48h to sector address with a7-a0 = 00011010 read from sector address with a7-a0 = 00011010 increment plscnt secsi sector entry secsi sector protection no no device failed data = 01h? yes yes secsi sector protection completed secsi sector exit write 555h/aah write 2aah/55ah write sa0+555h/90h write xxxh/00h secsi secto r exit plscnt = 25? figure 4. secsi sector protection algorithm
23 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. once the secsi sector is locked and veri ed, the system must write the exit secsi sector region command sequence to return to reading and writing the remainder of the array. the secsi sector lock must be used with caution since, once locked, there is no procedure available for unlocking the secsi sector area and none of the bits in the secsi sector memory space can be modi ed in any way. program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 3 ns (typical) on oe#, cs#, or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , cs# = v ih or we# = v ih . to initiate a write cycle, cs# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = cs# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up. common flash memory interface (cfi) the common flash interface (cfi) speci cation outlines device and host system software interrogation handshake, which allows speci c vendor-speci ed software algorithms to be used for entire families of devices. software support can then be device-independent, jedec id-independent, and forward- and backward-compatible for the speci ed ash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h, any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 9 ? 12 . to terminate reading cfi data, the system must write the reset command. the cfi query mode is not accessible when the device is executing an embedded program or embedded erase algorithm. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 9 ? 12 . the system must write the reset command to return the device to reading array data. write 60h to any address write 40h to secsi sector address with a6 = 0, a1=1,a0=0 reset# = v ih or v id wait 1 s read from secsi sector address with a6 = 0, a1=1,a0=0 if data = 00h, secsi sector is unprotected. if data = 01h, secsi sector is protected. remove v ih or v id from reset# write reset command secsi sector protect verify complete start secsi sector protection bits the secsi sector protection bits prevent programming of the secsi sector memory area. once set, the secsi sector memory area contents are non-modi able. hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal figure 5. secsi sector protect verify
24 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. table 9. cfi query identification string addresses data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string "qry" 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists) table 10. system interface string addresses data description 1bh 0027h vcc min. (write/erase) d7-d4: volt, d3-d0: 100 millivolt 1ch 0036h vcc max. (write/erase) d7-d4: volt, d3-d0: 100 millivolt 1dh 0000h vpp min. voltage (00h = no vpp pin present) 1eh 0000h vpp max. voltage (00h = no vpp pin present) 1fh 0004h typical timeout per single byte/word write 2 n s 20h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 0009h typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0005h max. timeout for byte/word write 2 n times typical 24h 0000h max. timeout for buffer write 2 n times typical 25h 0004h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
25 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. table 11. device geometry definition addresses data description 27h 0018h device size = 2 n byte 28h 29h 0001h 0000h flash device interface description 2ah 2bh 0000h 0000h max. munber of byte in multi-byte write = 2 n (00h = not supported) 2ch 0003h number of erase block region within device 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 1 information 31h 32h 33h 34h 00fdh 0000h 0000h 0001h erase block region 2 information 35h 36h 37h 38h 0007h 0000h 0020h 0000h erase block region 3 information 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information
26 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. table 12. primary vendor-specific extended query addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string "pri" 43h 0031h major version number, ascii (re ects modi cations to the silicon) 44h 0033h minor version number, ascii (re ects modi cations to the cfi table) 45h 000ch address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon revision number (bits 7-2) 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 0007h sector protect/unprotect scheme 01 = 29f040 mode, 02 = 29f016 mode, 03 = 29f400, 04 = 29lv800 mode 4ah 00e7h simultaneous operation 00 = not supported, x = number of sectors excluding bank 1 4bh 0000h burst mode type 00 = not supported, 01 = supported 4ch 0002h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 0085h acc (acceleration) supply minimum 00h = not supported, d7-d4; volt, d3-d0: 100 mv 4eh 0095h acc (acceleration) supply maximum 00h = not supported, d7-d4; volt, d3-d0: 100 mv 4fh 0001h top/bottom boot sector flag 00h = uniform device, 02h = bottom boot device, 03 = top boot device, 04h = both top and bottom 50h 0001h program suspend 0 = not supported, 1 = supported 57h 0004h bank organization 00 = data at 4ah is zero, x = number of banks 58h 0027h bank 1 region information x = number of sectors in bank 1 59h 0060h bank 2 region information x = number of sectors in bank 2 5ah 0060h bank 3 region information x = number of sectors in bank 3 5bh 0027h bank 4 region information x = number of sectors in bank 4
27 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. command definitions writing speci c address and data commands or sequences into the command register initiates device operations. table 13 de nes the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. a reset command is then required to return the device to reading array data. all addresses are latched on the falling edge of we# or cs#, whichever happens later. all data is latched on the rising edge of we# or cs#, whichever happens rst. refer to the ac characteristic section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. each bank is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the corresponding bank enters the erase-suspend- read mode, after which the system can read data from any non-erase- suspended sector within the same bank. the system can read array data using the standard read timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see the erase suspend/erase resume commands section for more information. the system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. see the next section, reset command , for more information. see also requirements for reading array data in the device bus operations section for more information. the ac characteristic table provides the read parameters, and figure 11 shows the timing diagram. reset command writing the reset command resets the banks to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the bank to which the system was writing to the read mode. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the bank to which the system was writing to the read mode. if the program command sequence is written to a bank that is in the erase suspend mode, writing the reset command returns that bank to the erase-suspend- read mode. once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if a bank entered the autoselect mode while in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. the autoselect command sequence may be written to an address within a bank that is either in the read or erase- suspend-read mode. the autoselect command may not be written while the device is actively programming or erasing in the other bank. the autoselect command sequence is initiated by rst writing two unlock cycles. this is followed by a third write cycle that contains the bank address and the autoselect command. the bank then enters the autoselect mode. the system may read any number of autoselect codes without reinitiating the command sequence. table 13 shows the address and data requirements. to determine sector protection information, the system must write to the appropriate bank address (ba) and sector address (sa). table 4 shows the address range and bank number associated with each sector. the system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in erase suspend). enter secsi? sector/exit secsi sector command sequence the secsi sector region provides a secured data area containing a random, eight word electronic serial number
28 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. (esn). the system can access the secsi sector region by issuing the three-cycle enter secsi sector command sequence. the device continues to access the secsi sector region until the system issues the four-cycle exit secsi sector command sequence. the exit secsi sector command sequence returns the device to normal operation. the secsi sector is not accessible when the device is executing an embedded program or embedded erase algorithm. table 13 shows the address and data requirements for both command sequences. see also ?secsi? (secured silicon) sector flash memory region? for further information. note that the acc function and unlock bypass modes are not available when the secsi sector is enabled. word program command sequence programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and veri es the programmed cell margin. table 13 shows the address and data requirements for the program command sequence. note that the secsi sector, autoselect, and cfi functions are unavailable when a [program/erase] operation is in progress. when the embedded program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. the system can determine the status of the program operation by using dq7, dq6, or ry/by#. refer to the write operation status section for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause that bank to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was successful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to program data to a bank faster than using the standard program command sequence. the unlock bypass command sequence is initiated by rst writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. that bank then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the rst cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. table 13 shows the requirements for the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. (see table 14) the device offers accelerated program operations through the wp#/acc pin. when the system asserts v hh on the wp# acc pin, the device automatically enters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the wp#/acc pin to accelerate the operation. note that the wp#/acc pin must not be at v hh any operation other than accelerated programming, or device damage may result. in addition, the wp#/acc pin must not be left oating or unconnected; inconsistent behavior of the device may result. figure 6 illustrates the algorithm for the program operation. refer to the erase and program operations table in the ac characteristics section for parameters, and figure 16 for timing diagrams. chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device
29 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and veri es the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. table 13 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, dq2, or ry/by#. refer to the write operation status section for information on these status bits. any commands written during the chip erase operation are ignored. note that secsi sector, autoselect, and cfi functions are unavailable when a [program/erase] operation is in progress. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 7 illustrates the algorithm for the erase operation. refer to the erase and program operations tables in the ac characteristics section for parameters, and figure 17 section for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. table 13 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically programs and veri es the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time- out of 50 s occurs. during the time-out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase address and command following the exceeded time- out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re- enabled after the last sector erase command is written. any command other than sector erase or erase suspend during the time-out period resets that bank to the read mode. the system must rewrite the command sequence and any additional addresses and commands. note that secsi sector, autoselect, and cfi functions are unavailable when a [program/erase] operation is in progress. the system can monitor dq3 to determine if the sector erase timer has timed out (see the section on dq3: sector erase timer). the time-out begins from the rising edge of the nal we# pulse in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress figure 6. program operation
30 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing bank. the system can determine the status of the erase operation by reading dq7, dq6, dq2, or ry/by# in the erasing bank. refer to the write operation status section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 7 illustrates the algorithm for the erase operation. refer to the erase and program operations tables in the ac characteristics section for parameters, and figure 17 section for timing diagrams. erase suspend/erase resume commands the erase suspend command, b0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. the bank address is required when writing this command. this command is valid only during the sector erase operation, including the 80 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. addresses are ?don?t-cares? when writing the erase suspend command. after the erase operation has been suspended, the bank enters the erase-suspend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) reading at any address within erase-suspended sectors produces status information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status section for information on these status bits. after an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard word program operation. refer to the write operation status section for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. refer to the autoselect mode and autoselect command sequence sections for details. to resume the sector erase operation, the system must write the erase resume command (address bits are don?t care). the bank address of the erase-suspended bank is required when writing this command. further writes of the resume start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress notes: 1. see table 13 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer. figure 7. erase operation
31 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. command are ignored. another erase suspend command can be written after the chip has resumed erasing. password program command the password program command permits programming the password that is used as part of the hardware protection scheme. the actual password is 64-bits long. four password program commands are required to program the password. the system must enter the unlock cycle, password program command (38h) and the program address/data for each portion of the password when programming. there are no provisions for entering the 2-cycle unlock cycle, the password program command, and all the password data. there is no special addressing order required for programming the password. also, when the password is undergoing programming, simultaneous operation is disabled. read operations to any memory location will return the programming status. once programming is complete, the user must issue a read/reset command to return the device to normal operation. once the password is written and veri ed, the password mode locking bit must be set in order to prevent veri cation. the password program command is only capable of programming ?0?s. programming a ?1? after a cell is programmed as a ?0? results in a time-out by the embedded program algorithm? with the cell remaining as a ?0?. the password is all ones when shipped from the factory. all 64-bit password combinations are valid as a password. password verify command the password verify command is used to verify the password. the password is verifiable only when the password mode locking bit is not programmed. if the password mode locking bit is programmed and the user attempts to verify the password, the device will always drive all f?s onto the dq data bus. the password verify command is permitted if the secsi sector is enabled. also, the device will not operate in simultaneous operation when the password verify command is executed. only the password is returned regardless of the bank address. the lower two address bits (a1-a0) are valid during the password verify. writing the read/reset command returns the device back to normal operation. password protection mode locking bit program command the password protection mode locking bit program command programs the password protection mode locking bit, which prevents further veri es or updates to the password. once programmed, the password protection mode locking bit cannot be erased! if the password protection mode locking bit is veri ed as program without margin, the password protection mode locking bit program command can be executed to improve the program margin. once the password protection mode locking bit is programmed, the persistent sector protection locking bit program circuitry is disabled, thereby forcing the device to remain in the password protection mode. exiting the mode locking bit program command is accomplished by writing the read/reset command. persistent sector protection mode locking bit program command the persistent sector protection mode locking bit program command programs the persistent sector protection mode locking bit, which prevents the password mode locking bit from ever being programmed. if the persistent sector protection mode locking bit is veri ed as programmed without margin, the persistent sector protection mode locking bit program command should be reissued to improve program margin. by disabling the program circuitry of the password mode locking bit, the device is forced to remain in the persistent sector protection mode of operation, once this bit is set. exiting the persistent protection mode locking bit program command is accomplished by writing the read/reset command. secsi sector protection bit program command the secsi sector protection bit program command programs the secsi sector protection bit, which prevents the secsi sector memory from being cleared. if the secsi sector protection bit is veri ed as programmed without margin, the secsi sector protection bit program command should be reissued to improve program margin. exiting the v cc -level secsi sector protection bit program command is accomplished by writing the read/reset command.
32 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. ppb lock bit set command the ppb lock bit set command is used to set the ppb lock bit if it is cleared either at reset or if the password unlock command was successfully executed. there is no ppb lock bit clear command. once the ppb lock bit is set, it cannot be cleared unless the device is taken through a power-on clear or the password unlock command is executed. upon setting the ppb lock bit, the ppbs are latched into the dybs. if the password mode locking bit is set, the ppb lock bit status is re ected as set, even after a power-on reset cycle. exiting the ppb lock bit set command is accomplished by writing the read/ reset command (only in the persistent protection mode). dyb write command the dyb write command is used to set or clear a dyb for a given sector. the high order address bits (a22?a12) are issued at the same time as the code 01h or 00h on dq7-dq0. all other dq data bus pins are ignored during the data write cycle. the dybs are modi able at any time, regardless of the state of the ppb or ppb lock bit. the dybs are cleared at power-up or hardware reset. exiting the dyb write command is accomplished by writing the read/reset command. password unlock command the password unlock command is used to clear the ppb lock bit so that the ppbs can be unlocked for modi cation, thereby allowing the ppbs to become accessible for modi cation. the exact password must be entered in order for the unlocking function to occur. this command cannot be issued any faster than 2 s at a time to prevent a hacker from running through all 64-bit combinations in an attempt to correctly match a password. if the command is issued before the 2 s execution window for each portion of the unlock, the command will be ignored. once the password unlock command is entered, the ry/by# indicates that the device is busy. approximately 1 s is required for each portion of the unlock. once the rst portion of the password unlock completes (ry/by# is not low or dq6 does not toggle when read), the next part of the password is written. the system must thus monitor ry/by# or the status bits to con rm when to write the next portion of the password. seven cycles are required to successfully clear the ppb lock bit. ppb program command the ppb program command is used to program, or set, a given ppb. each ppb is individually programmed (but is bulk erased with the other ppbs). the speci c sector address (a22?a12) are written at the same time as the program command 60h with a6 = 0. if the ppb lock bit is set and the corresponding ppb is set for the sector, the ppb program command will not execute and the command will time-out without programming the ppb. after programming a ppb, two additional cycles are needed to determine whether the ppb has been programmed with margin. if the ppb has been programmed without margin, the program command should be reissued to improve the program margin. also note that the total number of ppb program/erase cycles is limited to 100 cycles. cycling the ppbs beyond 100 cycles is not guaranteed. the ppb program command does not follow the embedded program algorithm. all ppb erase command the all ppb erase command is used to erase all ppbs in bulk. there is no means for individually erasing a speci c ppb. unlike the ppb program, no speci c sector address is required. however, when the ppb erase command is written all sector ppbs are erased in parallel. if the ppb lock bit is set the all ppb erase command will not execute and the command will time-out without erasing the ppbs. after erasing the ppbs, two additional cycles are needed to determine whether the ppb has been erased with margin. if the ppbs has been erased without margin, the erase command should be reissued to improve the program margin. it is the responsibility of the user to preprogram all ppbs prior to issuing the all ppb erase command. if the user attempts to erase a cleared ppb, over-erasure may occur making it dif cult to program the ppb at a later time. also note that the total number of ppb program/erase cycles is limited to 100 cycles. cycling the ppbs beyond 100 cycles is not guaranteed.
33 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. dyb write command the dyb write command is used for setting the dyb, which is a volatile bit that is cleared at reset. there is one dyb per sector. if the ppb is set, the sector is protected regardless of the value of the dyb. if the ppb is cleared, setting the dyb to a 1 protects the sector from programs or erases. since this is a volatile bit, removing power or resetting the device will clear the dybs. the bank address is latched when the command is written. ppb lock bit set command the ppb lock bit set command is used for setting the dyb, which is a volatile bit that is cleared at reset. there is one dyb per sector. if the ppb is set, the sector is protected regardless of the value of the dyb. if the ppb is cleared, setting the dyb to a 1 protects the sector from programs or erases. since this is a volatile bit, removing power or resetting the device will clear the dybs. the bank address is latched when the command is written. ppb status command the programming of the ppb for a given sector can be veri ed by writing a ppb status verify command to the device. ppb lock bit status command the programming of the ppb lock bit for a given sector can be veri ed by writing a ppb lock bit status verify command to the device. sector protection status command the programming of either the ppb or dyb for a given sector or sector group can be veri ed by writing a sector protection status command to the device. note that there is no single command to independently verify the programming of a dyb for a given sector group.
34 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. command definitions tables table 13. memory array command definitions command (notes) cycles bus cycles (notes 1-4) addr data addr data addr data addr data addr data addr data read (5) 1 ra rd reset (6) 1 xxx f0 autoselect (note 7) manufacturer id 4 555 aa 2aa 55 555 90 (ba)x00 04 device id (10) 6 555 aa 2aa 55 555 90 (ba)x01 7e (ba)x0e 20 (ba)x0f 00 secsi sector factory protect (8) 4 555 aa 2aa 55 555 90 x03 (see note 8) sector group protect verify (9) 4 555 aaa 2aa 55 555 90 (sa)x02 xx00/ xx01 program 4 555 aa 2aa 55 555 a0 pa pd chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend (11) 1 ba b0 program/erase resume (12) 1 ba 30 cfi query (13) 1 55 98 accelerated program (15) 2 xx a0 pa pd unlock bypass entry (15) 3 555 aa 2aa 55 555 20 unlock bypass program (15) 2 xx a0 pa pd unlock bypass erase (15) 2 xx 80 xx 10 unlock bypass cfi (13, 15) 1 xx 98 unlock bypass reset (15) 2 xxx 90 xxx 00 legend: ba = address of bank switching to autoselect mode, bypass mode, or erase operation. determined by a22:a20, see tables 4 and for more detail. pa = program address (a22:a0). addresses latch on falling edge of we# or cs# pulse, whichever happens later. pd = program data (dq15:dq0) for each chip written to location pa. data latches on rising edge of we# or cs# pulse, whichever happens rst. ra = read address (a22:a0). rd = read data (dq15:dq0) from location ra. sa = sector address (a22:a12) for verifying (in autoselect mode) or erasing. wd = write data. see ?con guration register? de nition for speci c write data. data latched on rising edge of we#. x = don?t care notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells in table denote read cycles. all other cycles are write operations. 4. during unlock and command cycles, when lower address bits are 555 or 2aah as shown in table, address bits higher than a11 (except where ba is required) and data bits higher than dq7 are don?t cares. 5. no unlock or command cycles required when bank is reading array data. 6. the reset command is required to return to reading array (or to erase-suspend-read mode if previously in erase suspend) when bank is in autoselect mode, or if dq5 goes high (while bank is providing status information). 7. fourth cycle of autoselect command sequence is a read cycle. system must provide bank address to obtain manufacturer id or device id information. see autoselect command sequence section for more information. 8. the data is c0h for factory and customer locked and 80h for factory locked. 9. the data is 00h for an unprotected sector group and 01h for a protected sector group. 10. device id must be read across cycles 4, 5, and 6. 11. system may read and program in non-erasing sectors, or enter autoselect mode, when in program/erase suspend mode. program/erase suspend command is valid only during a sector erase operation, and requires bank address. 12. program/erase resume command is valid only during erase suspend mode, and requires bank address. 13. command is valid when device is ready to read array data or when device is in autoselect mode. 14. wp#/acc must be at v id during the entire operation of command. 15. unlock bypass entry command is required prior to any unlock bypass operation. unlock bypass reset command is required to return to the reading array.
35 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. table 14. sector protection command definitions command (notes) cycles bus cycles (notes 1-4) addr data addr data addr data addr data addr data addr data addr data reset 1 xxx f0 secsi sector entry 3 555 aa 2aa 55 555 88 secsi sector exit 4 555 aa 2aa 55 555 90 xx 00 secsi protection bit program (5, 6) 6 555 aa 2aa 55 555 60 ow 68 ow 48 ow rd (0) sector protection bit status 5 555 aa 2aa 55 555 60 ow 48 ow rd(0) password program (5, 7, 8) 4 555 aa 2aa 55 555 38 xx[0-3] pd[0-3] password verify (6, 8, 9) 4 555 aa 2aa 55 555 c8 pwa[0-3] pwd[0-3] password unlock (7, 10, 11) 7 555 aa 2aa 55 555 28 pwa[0] pwd[0] pwa[1] pwd[1] pwa[2] pwd[2] pwa[3] pwd[3] ppb program (5, 6, 12) 6 555 aa 2aa 55 555 60 (sa)wp 68 (sa)wp 48 (sa)wp rd(0) ppb status 4 555 aa 2aa 55 555 90 (sa)wp rd(0) all ppb erase (5, 6, 13, 14) 6 555 aa 2aa 55 555 60 wp 60 (sa) 40 (sa)wp rd(0) ppb lock bit set 3 555 aa 2aa 55 555 78 ppb lock bit status (15) 4 555 aa 2aa 55 555 58 sa rd(1) dyb write (7) 4 555 aa 2aa 55 555 48 sa x1 dyb erase (7) 4 555 aa 2aa 55 555 48 sa x0 dyb status (6) 4 555 aa 2aa 55 555 58 sa 48 ppmlb program (5, 6, 12) 6 555 aa 2aa 55 555 60 pl 68 pl 48 pl rd(0) ppmlb status (5) 5 555 aa 2aa 55 555 60 pl 48 pl rd(0) spmlb program (5, 6, 12) 6 555 aa 2aa 55 555 60 sl 68 sl 48 sl rd(0) spmlb status (5) 5 555 aa 2aa 55 555 60 sl 48 sl rd(0) legend: dyb = dynamic protection bit ow = address (a7:a0) is (00011010) pd[3:0] = password data (1 of 4 portions) ppb = persistent protection bit pwa = password address. a1:a0 selects portion of password. pwd = password data being veri ed. pl = password protection mode lock address (a7:a0) is (00001010) rd(0) = read data dq0 for protection indicator bit. rd(1) = read data dq1 for ppb lock status. sa = sector address where security command applies. address bits a22:a12 uniquely select any sector. sl = persistent protection mode lock address (a7:a0) is (00010010) wp = ppb address (a7:a0) is (00000010) x = don?t care ppmlb = password protection mode locking bit spmlb = persistent protection mode locking bit 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells in table denote read cycles. all other cycles are write operations. 4. during unlock and command cycles, when lower address bits are 555 or 2aah as shown in table, address bits higher than a11 (except where ba is required) and data bits higher than dq7 are don?t cares. 5. the reset command returns device to reading array. 6. cycle 4 programs the addressed locking bit. cycles 5 and 6 validate bit has been fully programmed when dq0 = 1. if dq0 = 0 in cycle 6, program command must be issued and veri ed again. 7. data is latched on the rising edge of we#. 8. entire command sequence must be entered for each portion of password. 9. command sequence returns ffh if ppmlb is set. 10. the password is written over four consecutive cycles, at addresses 0-3. 11. a 2 s timeout is required between any two portions of password. 12. a 100 s timeout is required between cycles 4 and 5. 13. a 1.2 ms timeout is required between cycles 4 and 5. 14. cycle 4 erases all ppbs. cycles 5 and 6 validate bits have been fully erased when dq0 = 0. if dq0 = 1 in cycle 6, erase command must be issued and veri ed again. before issuing erase command, all ppbs should be programmed to prevent ppb overerasure. 15. dq1 = 1 if ppb locked, 0 if unlocked.
36 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 15 and the following subsections describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. the device also provides a hardware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or has been completed. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether a bank is in erase suspend. data# polling is valid after the rising edge of the nal we# pulse in the command sequence. during the embedded program algorithm, the device outputs on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for approximately 1 s, then that bank returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the bank enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately 400 s, then the bank returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if the system reads dq7 at an address within a protected sector, the status may not be valid. when the system detects dq7 has changed from the complement to true data, it can read valid data at dq15?dq0 on the following read cycles. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq15?dq0 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq15?dq0 may be still invalid. valid data on dq15?dq0 will appear on successive read cycles. table 15 shows the outputs for data# polling on dq7. figure 8 shows the data# polling algorithm. figure 19 in the ac characteristic section shows the data# polling timing diagram. dq7 = data? yes no no dq5=1? no yes yes pass read dq7?dq0 addr=va read dq7?dq0 addr = va dq7 = data? start fail notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5. figure 8. data# polling algorithm
37 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the nal we# pulse in the command sequence. since ry/by# is an open-drain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-suspend- read mode. table 15 shows the outputs for ry/by#. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the nal we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cycles to any address cause dq6 to toggle. the system may use either oe# or cs# to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 400 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7 (see the subsection on dq7: data# polling ). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. table 15 shows the outputs for toggle bit i on dq6. figure 9 shows the toggle bit algorithm. figure 20 in the ?ac characteristics? section shows the toggle bit timing diagrams. figure 21 shows the differences between dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii . start no yes yes dq5=1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete toggle bit = toggle? read byte twice (dq7?dq0) address = va read byte (dq7?dq0) address =va read byte (dq7?dq0) address =va note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information. figure 9. toggle bit algorithm
38 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the nal we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe# or cs# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table 15 to compare outputs for dq2 and dq6. figure 9 shows the toggle bit algorithm in owchart form, and the section ?dq2: toggle bit ii? explains the algorithm. see also the dq6: toggle bit i subsection. figure 20 shows the toggle bit timing diagram. figure 21 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 9 for the following discussion. whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the rst read. after the second read, the system would compare the new value of the toggle bit with the rst. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 9). dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a speci ed internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the timing limit has been exceeded, dq5 produces a ?1.? under both these conditions, the system must write the reset command to return to the read mode (or to the erase- suspend-read mode if a bank was previously in the erase- suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. table 15 shows the status of dq3 relative to the other status bits.
39 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. table 15. write operation status status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspend mode erase-suspend- read erase suspended sector 1 not toggle 0 n/a toggle 1 non-erase suspend sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0 notes: 1. dq5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. when reading write operation status bits, the system must always provide the bank address where the embedded algorithm is in progress. the device outputs array data if the system addresses a non-busy bank
40 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. absolute maximum ratings (1, 2) parameter unit operating temperature -55 to +125 c supply voltage range (v cc ) -0.5 to +4.0 v storage temperature range -55 to +125 c endurance (write/erase cycles) 1,000,000 min. cycles notes: 1. stesses above the absolute maximum rating may cause permanent damage to the device. extended operation at the maximum levels may degrade performance and affect reliability. 2. minimum dc input voltage on pins a9, oe#, reset#, and wp#/acc is ?0.5v. during voltage transitions, a9, oe#, wp#/acc, and reset# may overshoot v ss to ?2.0v for periods of up to 20 ns. see figure 8 . maximum dc input voltage on pin a9, oe#, and reset# is +12.5v which may overshoot to +14.0v for periods up to 20 ns. maximum dc input voltage on wp#/acc is +9.5v which may overshoot to +12.0v for periods up to 20 ns. recommended operating conditions parameter symbol min max unit supply voltage v cc 3.0 3.6 v i/o supply voltage v io 3.0 3.6 v operating temp. (mil.) t a -55 +125 c operating temp. (ind.) t a -40 +85 c note: for all ac and dc speci cations: v io = v cc capacitance t a = +25c, f = 1.0mhz parameter symbol max unit we# capacitance c we 12 pf cs# capacitance c cs 13 pf data i/o capacitance c i/o 13 pf address input capacitance c ad 35 pf reset# capacitance c rs 35 pf ry/by# c rb 32 pf oe# capacitance c oe 36 pf this parameter is guaranteed by design but not tested. data retention parameter test conditions min unit pattern data retention time 150c 10 years 125c 20 years
41 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. dc characteristics - cmos compatable v cc = 3.3v 0.3v. -55c t a +125c parameter description symbol test conditions min max unit input load current (addresses) i li v in =v ss to v cc , v cc =v cc max -4 4 a output leakage current i lo v out = v ss to v cc , oe# = v ih , v cc = v cc max -1 1 a v cc active read current (notes 1, 2) l cc1 oe# = v ih , v cc = v cc max, f = 5 mhz (note 1) 120 ma v cc active write current (notes 2, 3) i cc2 oe# = v ih , we# =v il 100 ma v cc standby current (note 2) l cc3 cs#, reset#, wp/acc# = v io 0.3 v 150 a automatic sleep mode (notes 2, 4, 5) i cc5 v ih = v io 0.3 v; v il = v ss 0.3 v 150 a v cc active read-while-program current (notes 1, 2, 5) i cc6 oe# = v ih 180 ma v cc active read-while-erase current (notes 1, 2, 5) i cc7 oe# = v ih 180 ma input low voltage v il v io = 3.3v 0.3v -0.5 0.8 v input high voltage v ih v io = 3.3v 0.3v 2.0 v cc +0.3 v voltage for acc program acceleration v hh v cc = 3.0 v 0.3v 8.5 9.5 v voltage for autoselect and temporary sector unprotect v id vcc = 3.0 v 0.3v 11.5 12.5 v output low voltage v ol i ol = 2.0 ma, v cc = v cc min , v io = 3.3v 0.3v 0.4 v output high voltage v oh i oh = -2.0 ma, v cc = v cc min , v io = 3.3v 0.3v 2.4 v low v cc lock-out voltage (note 5) v lko 2.3 2.5 v notes: 1. the l cc current listed is typically less than 5 ma/mhz, with oe# at v ih . 2. maximum l cc speci cations are tested with v cc = v ccmax. 3. i cc active while embedded erase or embedded program is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 150 ns. typical sleep mode current is 4 a. 5. not tested.
42 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. current source current source i ol i oh d.u.t. c = 50 pf eff v ~ 1.5v (bipolar supply) z ac test circuit fig 10: ac test conditions parameter typ unit input pulse levels v il - 0, v ih = 2.5 v input rise and fall 5 ns input and output reference level 1.5 v output timing reference level 1.5 v notes: vz is programmable from -2v to +7v. iol & ioh programmable from 0 to 16 ma. tester impedance z0 = 50 . vz is typically the midpoint of v oh and v ol. iol & ioh are adjusted to similate a typical resistive load circuit. ate tester includes jig capacitance. ac characteristics - read-only operations v cc = 3.3v 0.3v, -55c t a +125c parameter symbol -70min max -90 min max -100 min max -120 min max unit read cycle time (1) t avav t rc 70 90 100 120 ns address access time t avqv t acc 70 90 100 120 ns chip select access time t elqv t ce 70 90 100 120 ns page access time (1) t pacc 25 25 100 120 ns output enable to output valid t olqv t oe 30 40 40 50 ns chip select high to output high z t ehqz t df 20 20 20 20 ns output enable high to output high z t ghqz t df 20 20 20 20 ns output hold from addresses, cs# or oe# change, whichever occurs rst t axqx t oh 555 ns output enable hold time (1) read t oeh 000 toggle and data# polling 10 10 10 note: 1. not tested.
43 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. a ddresses addresses stable t rc t acc t oe t oeh t ce t df t oh high z high z t rh cs# oe# we# outputs reset# ry/by# output valid ov a 22-a3 a2-a0 data cs# oe# aa ab ac ad qa qb qc qd same page t acc t pacc t pacc t pacc fig 11: ac waveforms for read operations fig 12: page read operation timings
44 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. ac characteristics - hardware reset (1) parameter symbol min max unit reset# pin low (during embedded algorithms) to read mode t ready 20 s reset# pin low (not during embedded algorithms) to read mode t ready 500 ns reset# pulse width t rp 500 ns reset# high time before read t rh 50 ns reset# low to standby mode t rpd 20 s ry/by# recovery time t rb 0ns note: 1. not tested. reset# ry/by# ry/by# t rp t ready t ready cs#, oe# t rh cs#, oe# reset# t rp t rb fig. 13: reset timings not during embedded algorithms fig. 14: reset timings during embedded algorithms
45 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. ac characteristics - write/erase/program operations - we# controlled v cc = 3.3v 0.3v, -55c t a +125c parameter symbol -70 min max -90 min max -100 min max -120 min max unit write cycle time (3) t avav t wc 70 90 100 120 ns chip select setup time (3) t elwl t cs 000 0 ns write enable pulse width t wlwh t wp 35 35 50 50 ns address setup time t avwl t as 000 0 ns data setup time t dvwh t ds 45 45 50 50 ns data hold time t whdx t dh 000 0 ns address hold time t wlax t ah 45 45 50 50 ns write enable pulse width high (3) t whwl t wph 20 30 30 30 ns duration of byte programming operation (1) t whwh1 300 300 300 300 s sector erase (2) t whwh2 5 5 5 5 sec read recovery time before write (3) t ghwl 000 0 ns v cc setup time (3) t vcs 50 50 50 50 s chip programming time (4) 200 200 200 200 sec address setup time to oe# low during toggle bit polling t aso 15 15 15 15 ns write recovery time from ry/by# (3) t rb 000 0 ns program/erase valid to ry/by# t busy 70 90 90 90 ns notes: 1. typical value for t whwh1 is 6 s. 2. typical value for t whwh2 is 0.5 sec. 3. guaranteed by design, but not tested. 4. typical value is 50 sec. the typical chip program time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed.
46 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. fig. 15: program operation oe# we# cs# v data cc a ddresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa notes: 1. pa is the address of the memory location to be programmed. 2. pd is the data to be programmed at byte address. 3. d out is the output of the data written to the device.
47 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. fig 16: acceletated program timing diagram wp#/acc t vhh v hh vorv il ih vorv il ih t vhh fig 17: chip/sector erase operation timings oe# we# cs# v data cc a ddresses t ds t ah t dh t wp 30h t whwh2 t wc t as t wph t vcs 2aah sa va read status data (last two cycles) 55h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch va 10 for chip erase 555h for chip erase notes: 1. sa = sector address (for sector erase), va = valid address for reading status data (see "write operation status")
48 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. fig 19: data# polling timings (during embedded algorithms) fig 18: back to back read/write cycle timings oe# cs# we# a ddresses t oh data valid in valid in valid pa valid ra t wc t wph t ah t wp t ds t dh t as t rc t cs t ah valid out t oe t acc t oeh t ghwl t df valid in cs# controlled write cycles we# controlled write cycle valid pa valid pa t cp t cph t wc t wc read cycle t sr/w t as we# cs# oe# high z t oe high z dq7 dq6?dq0 ry/by# t busy complement tr u e a ddresses va t oeh t cs t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc note: va = valid address. illustration shows rst status cycles after command sequence, last status read cycles, and array data read cycle.
49 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. fig 21: dq2 vs. dq6 fig 20: toggle bit timings (during embedded algorithms) oe# cs# we# a ddresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t csph t aht t as dq6/dq2 valid data valid status valid status valid status ry/by# enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or cs# to toggle dq2 an d dq6.
50 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. notes: for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0. fig 22: sector/sector block protect and unprotect timing diagram sector group protect: 150 s sector group unprotect: 15 m s 1s reset# sa, a6 , a1, a 0 data cs# we# oe# 60h 60h 40h valid * valid * valid * status sector group protect/unprotec t verif y v id v ih ac characteristics - alternate cs# controlled erase and program operations parameter description speed options unit jedec std 70 90 100 120 t vavav t ws write cycle time (1) min 70 90 100 120 ns t avwl t as address setup time min 0 0 0 0 ns t elax t ah address hold time min 45 45 45 50 ns t dveh t ds data setup time min 45 45 45 50 ns t ehdx t dh data hold time min 0 0 0 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 0 0 0 ns t wlel t ws we# setup time min 0 0 0 0 ns t ehwh t wh we# hold time min 0 0 0 0 ns t eleh t cp cs# pulse width min 35 35 45 50 ns t ehel t cph cs# pulse width high (1) min 30 30 30 30 ns t whwh1 t whwh1 programming operation typ 6 6 6 6 s t whwh1 t whwh1 accelerated programming operation typ 4 4 4 4 s t whwh2 t whwh2 sector erase operation typ 0.5 0.5 0.5 0.5 sec note: 1. not tested.
51 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. fig 23: alternate cs# controlled write (erase/program) operation timings t ghel t oe# ws cs# we# reset# t data ds t a ddresses ah t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy notes: 1. figure indicated last two bus cycles of a program or erase operation. 2. pa = program address. sa = sector address, pd = program data. 3. dq7 is the complement of the data written to the device. d out is the data written to the device.
52 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. temporary sector unprotect parameter description all speed options unit jedec std t vidr v id rise and fall time (see note) min 500 ns t vhh v hh rise and fall time (see note) min 250 ns t rsp reset# setup time for temporary sector unprotect min 4 s t rrb reset# hold time from ry/by# high for temporary sector unprotect min 4 s note: not tested. reset# t vidr v id v il or v ih v id v il or v ih ce# we# ry/by# t vidr t rsp program or erase command sequence t rrb fig 24: temporary sector unprotect timing diagram
53 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. package: 159 pbga (plastic ball grid array) 987654321 10 a b c d e f g h j k l m n p r t 22.15 (0.872) max 19.05 (0.750) nom 1.27 (0.050) nom 1.27 (0.050) nom 11.43 (0.450) nom 13.15 (0.518) max 0.61 (0.024) nom 2.34 (0.092) max 159 x ? 0.762 (0.030) nom bottom view all linear dimensions are in millimeters and parenthetically in inches ordering information w 7 8m64 v xxx sb x white eletronic designs corp. flash: organization, 8m x 64: user con gurable as 2 x 8m x 32, or 4 x 8m x16 3.3v power supply: access time (ns): 70 = 70ns 90 = 90ns 100 = 100ns 120 = 120ns package type: sb = 159 pbga, 13mm x 22mm devise grade: m = military -55c to +125c i = industrial -40c to +85c c = commercial 0c to +70c .
54 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs w78m64v-xsbx july 2006 rev. 4 white electronic designs corp. reserves the right to change products or speci cations without notice. document title 8mx64 flash 3.3v page mode simultaneous read/write operations multi-chip package revision history rev # history release date status rev 0 initial release june 2004 advanced rev 1 changes (pg. 1, 54) 1.1 change status to preliminary october 2004 preliminary rev 2 changes (pg. 1, 41) 2.1 pcn# 05006 april 2005 preliminary rev 3 changes (all pages) 3.1 change status to final 3.2 add 70 ns speed grade 3.3 correct manufacturer id 3.4 add capacitance data 3.5 add v io to recommended operating conditions 3.6 change ili to -4 and 4 a 3.7 remove duplicate read operations table 3.8 add we# controlled program table december 2005 final rev 4 changes (pg.1, 41, 42,45, 54) 4.1 correct typo in dc charcteristics table v oh condition v cc = v cc min 4.2 ac test conditions tester impedance z0 = 50 4.3 correct typos in ac characteristics read-only operations table t avaqv to t avqv and t glqv to t olqv 4.4 change t pacc to 25ns for 70 and 90ns speed grades 4.5 change t ds and t ah to 45ns min for 70ns speed grade, this was a typographical change. july 2006 final

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